Hardware-compiler co-design for adjustable data power savings

To accomodate standards changes and algorithmic improvements, functional reconfigurability is increasingly desired for media processing. Such adaptability, however, generally comes at significant power cost. This work suggests that another dimension of adaptation can be beneficial – power adaptation. Through a unique compiler–hardware approach, we (1) demonstrate an extension to the state-of-theart in data analyzability, yielding better control over scratchpad data management, and (2) combine this knowledge with an SRAM having variable latency and access properties, yielding adjustable power savings. Building upon the compiler techniques presented in [1], we evaluate the severity of the current on-chip storage power problem and detail how SRAM structures can be built to enable data power savings for media applications. We show how the implemented compiler techniques can be applied to other problems in the embedded/media processing domain, and present net data power savings results for a suite of media and telecommunication applications, including MPEG-2, MPEG-4, H.263, and JPEG-2000.